Bridge driver h

I have a question on cascading an H bridge. Is it possible to cascade an H bridge that can switch the current e. Cascading H-bridges is a really bad idea. For one, it will limit current delivery to the lowest of any of the bridges. On top of that it will most likely not work at all. Putting bridges in parallel might work, but there are a lot of pit-falls there as well, and driving them all with the same PWM input is a must. The best way though is to have a single H-bridge, capable of driving the right amount of current.

Since 3A and 1A are not all that different, can you maybe upgrade the power transistors in your old bridge to help with the increased current? As you said, the current requirements are not that drastically different, so the driver of the gates is probably capable of driving the more powerfull FETS.

I have a unique problem I would like insight too. It has been an electronic mystery to me — and ideas are running short. I have an H-Bridge design I am looking into. The device can run from a battery or wall adapter. There are several interesting things about this failure. The N has a higher Id rating than that of the P. The bridge suffers from a conduction issue in its design.

The switching on FETs input C feeds back to distort the unintended off leg — making for momentary conduction. And it does happen on both sides. The bridge drives a motor. The motor stalled can only draw. When operated from wall adapter the wall adapter does not supply enough current even at its peak SC to be the issue. The SC current peaks at about 4.

What would be causes whereby I have the same FET to fail and not others. MOSFETs are very sensitive to this and even a momentary violation that can happen due to capacitive coupling for example can destroy the device. You can do that by connecting a resistor between the FETs gate and source. As to why again, predicated on me being right about the cause this only impacts the low-side: P-channel MOSFETs for the same current rating Rdson are typically bigger then the equivalent N-channel device.

This in turn means higher gate-capacitance. If there is indeed capacitive coupling, the parasitic capacitance and the gate capacitance forms a capacitive divider, which would result in a lower peak voltage on the P-channel part then in the N-channel for the same amount of aggression. So the N-channel device would see a Vgs violation sooner than the P-channel part would be. A million thanks for taking my question!!!

Regarding paragraph 1 of your response a resistor added between the FET D and S, would have to be a very high value to not look like a leakage on condition. To decrease coupling back into the control circuit I introduced a resistor in the gate of the FET — there a sweet spot that has to be found that reduces the feedback, but does not overly slow the FET at stated PWM. It worked well in circuit and in simulation — though I would admit it looks a little strange in schematic. All the same my real goal is to find root cause of the problem.

Are you referring to a coupling path at the point of where the N and P Ds meet feeding back onto the Gs of said devices with the transient coming from the motor, or are you referring to a transient coming from the supply and being passed more effectively to the gate of the N. I am missing the cap divider concept here — assuming the parasitic cap you make reference to is the Cgd and Cgs.

The second paragraph was a theory as to why the low-side FET is going bust. If you have noise coupling into the gate of either FETs capacitively, there is always a capacitive divider between that parasitic coupling capacitance and the gate capacitance along with any other things connected to the gate, for example the driver output capacitance. For the same low-side FET to fail all the time — to state the obvious — there must be an asymmetry somewhere in the system.

This might not be in the circuit though: for example if you mostly drive the motor in one direction, the circuit is used in an asymmetrical way, even if it itself is totally symmetrical.

The current regulation of that driver will always keep it at the setted value despite of the resistors that you put in series with the motor. Hello, Why the interchange of the values of Isource and Isink in determining the turn on time and turn off time? Your email address will not be published. Save my name, email, and website in this browser for the next time I comment. Notify me of followup comments via e-mail. You can also subscribe without commenting. It has two major purposes: Translate the input voltages to suitable levels to drive the gates Provide enough current to charge and discharge the gates fast enough On top of that, many drive circuits include additional functionality: Translate the input command into gate-drive signals according to the drive mode Provide shoot-through protection Generate voltages for the high-side gate-drive circuitry for N-channel drivers Provide additional safety functions, like over-current protection Control the turn-on and turn-off times of the FETs Drive circuits can come in many shape or form.

There are low-side drivers, that are designed to drive Q2 or Q4 on our bridge. High-side drivers in turn are designed to drive Q1 or Q3. Half-bridge drivers combine one low- and one high-side driver, so they can drive Q1 and Q2 or Q3 and Q4 together. Full-bridge drivers obviously have two low-side and two high-side drivers so they can drive all four FETs.

In case you were wondering how is this driver stage different from one side of an H-bridge: The FETs are much smaller, so their gate capacitance is really small. Even a relatively weak source can quickly charge and dis-charge them. These smaller FETs also have a much higher r dson value several ohms so the dynamic shoot-through currents are low enough not be a headache. It is usually specified in the form of a chart like this this is from Wikipedia : As you can see, for relatively low drain-currents Y axis the FET operates as a small resistance the curve is linear and goes through the origin.

Driver characteristics are usually quite complex, and they are specified using charts, like this: Here you see how the output current changes as the function of the output voltage, or the more useful way of looking at it: if you want to draw a certain amount of current out of the pin, how much the output voltage will deviate from its ideal value.

Constant current drivers The constant current approach works the following way: we try to charge up a capacitor with a constant current source to at least a certain voltage.

Piece-wise linear model A more precise estimate can be made by combining the two methods, and assume constant current charge and discharge until the knee-point 2. Controlling turn-on and off times So far so good, we have several ways now to calculate the transient times, with various accuracy.

By far the most common way of controlling the trun-on and —off times is to add a series resistor to the driver outputs: The series resistor method is ineffective if the driver is truly a current source, but that very rarely is the case.

Low-side drivers In the following I will only deal with one-half of the bridge. The question is: what to put in the place of the mystery circuit: The simplest drive circuitry: none For very simple, low-voltage designs, they might be completely missing, and the FETs are directly driven by logic level signals.

This technique however only works under limited circumstances: You have to make sure that the output voltages of the digital logic are in fact capable of turning the FET fully on.

One of the simplest level shifters is this: Here, the gate of the small-signal N-FET is driven by a suitable logic signal and a logic level signal can easily turn this N-FET on and the drain of it is pulled up to the gate-drive power supply, V drive. To overcome this problem, an complementer driver stage can be added between the level shifter and the power-FET: This stage will make both the high- and low-level drive strength roughly equal, consequently making the turn-on and —off times much closer to one another.

This is usually accomplished by adding a Zener diode to the drive circuit: If you set the Zener voltage to about 15V, it will limit your voltage difference between the output and V bat to be within the safe limits.

In most cases some kind of a charge-pump is used for that generation, mostly in a boot-strapped configuration: While actual implementations could be quite a bit more complex, I will use this simplified variant to explain how things work. D boot , which is connected between V cc and the other side of C boot will make sure that C boot is charged up to V cc : This of course also means that V boot is equal to V cc , 12V in our example.

Normally, C boot would discharge quickly towards V cc , but in our case D boot closes and lets V boot rise as high as it wishes: At that point V out is at V bat and V boot is higher than that by V cc 12V. Conclusion This was a loooong article I have to admit, but hopefully it gives you some background into the design challenges of the drive circuitry of H-bridges. Thanks again, Andras. It will blow your FET. Really I thank you very much for such information..

Regards, Andras Tantos. Hi, very interesting and useful article! My congratulations. Thank you for your feedback! Andras Tantos. Hi Andras, for what I know the main drawback of the bootstrap-like drivers is the negative voltage spikes they can tolerate on the source terminal, so basically they cannot be used at all in an application where you need split supply positive and negative at the bridge legs.

Thank you Maurizio. Thanks again! I hope this helps, Andras. I have to questions: 1- How do we find the output resistance of gate driver that does not provide you with output voltage and current in the same graph? Thanks for the comment! Please do send a diagram. From this description I have no idea what the problem could be. Hi Andras, thanks for looking into this! I am missing the cap divider concept here — assuming the parasitic cap you make reference to is the Cgd and Cgs Lastly not only is it the N that is failing it is always the same N not the other.

Look forward to Hearing from you. Good point, and it was a mistake. We use these ICs in autonomous robots mainly to control them. For example the popular Arduino microcontrollers or PIC microcontroller has an operating voltage of 5V or 3. In this case if we want to supply the power to the motor, we need a high voltage. Motor driver receives signals from the microprocessor and eventually, it transmits the converted signal to the motors.

It has two voltage pins VCC1 and VCC2 , and one of them is used to turn on the motor driver, and another pin is used to apply the voltage to the motor through this motor IC. This motor IC will continuously toggle the output signal according to the input wave it is receiving from the microprocessor.

The small IC transmits the signal it receives, but it will not change the value of the signal. For example, if the microprocessor sends a high input 1 to the Driver Ic then, driver Ic will pass the same High 1 though it's an output pin. The H-bridge circuit will look like this in the picture below. Rotate in clockwise direction. Now, in the first condition, when S1 and S4 switches are closed, and S3 and S2 are open, the voltage will pass from the S1 switch to the Motor and then to the S4.

Hence we have a complete circuit that will allows current to flow from V to M through S1 and S4. This state will be a short circuit in S1 and S4 switch condition. In this case, the Motor will be in ON, and the direction of the Motor will be in a clockwise rotation. Unfortunately, when using an H-bridge circuit, a single flyback diode will not suffice.

Since there are multiple current pathways, there must be four diodes to provide a path for the induced voltage as shown in Figure 5. No matter the direction of the motor or the induced voltage, it always has a safe pathway to go through the power rail. Figure 5: Completed H-Bridge circuit with flyback protection. Since this is a simple circuit , I will not go over the PCB layout in this post, as my implementation is in part two of the video series: Video.

This post covered the basics of what an H-Bridge circuit is and the various ways in which they can be implemented. For the circuit created here, we used an integrated H-Bridge, which allows for a more simplistic design, with fewer external parts required.

Since the IC chosen had no protection from inductive loads, we discussed the proper way to protect the circuit. MicroType Engineering strives to help businesses turn an idea into a physical product. Whether you are already established and seeking to branch out into a new product or working on an exciting new startup project, MTE can guide you along the way. MTE provides rapid prototyping, enabling you to quickly have a physical product in your hands to showcase and test. MTE offers a personalized approach, helping navigate the often confusing, and expensive path to manufacturing and selling a product.

Contact us to learn more. Call Us Now that we have handled the inductive load issue, the rest of the circuit is quite straightforward. For this circuit, it is intended to be a standalone board, using an external microcontroller such as an Arduino or Raspberry PI. Figure 6 shows the completed circuit, using global labels to connect the majority of the nets from one component to the other.